In testing semiconductor devices such as IC memories and IC processors by a semiconductor test system, test patterns are supplied to the semiconductor device under test and resultant outputs of the semiconductor device are compared with expected value patterns to determine whether the semiconductor device functions correctly or not. The test patterns and expected value patterns including associated control data are frequently called test vectors in the semiconductor test industry because the major portion of the patterns are repetitive based on, for example, a mathematical algorithm.
Generally, such test patterns and expected value patterns (collectively "test patterns") are generated by a test pattern generator provided in the semiconductor test system under the control of a test controller provided in the test system. Test patterns are unique to the types of semiconductor device or the kinds of device test. The test patterns are usually stored in a hard disk of a host computer, such as a Unix host, or external storage devices. The test pattern generator has a pattern memory with a large memory capacity to store the test patterns. Thus, prior to the test, the test pattern is transferred from the hard disk of the host computer to the pattern memory in the pattern generator through the test controller.
FIG. 1 shows a basic structure of a semiconductor test system. A host computer 11 is a user accessible computer whose operating system is, for example, Unix. A hardware semiconductor test system 10 includes a pattern generator 15, a wave formatter 17 and a comparator 19. The hardware test system (tester) 10 is directly controlled by a tester controller (TC) 13. The tester controller 13 is a computer exclusive to the semiconductor tests system 10 and not directly controlled by the user. A semiconductor device 12 under test (DUT) receives a test pattern through the wave formatter 17 and the resultant output signals are compared with an expected value pattern by the comparator 19.
The pattern generator 15 includes a pattern memory 18 to store test patterns (test patterns and expected value patters) transferred from the host computer 11 through the test controller 13 and a tester bus 14. The test patterns are usually stored in a hard disk 16 of the host computer 11 as pattern files and transferred to the pattern memory prior to the start of the testing.
Such a transfer of test patterns occur frequently when devices to be tested are changed or different test programs are executed. The size of the pattern files may be several megabytes or several tens of megabytes, or more, because of the complexities of modern semiconductor devices to be tested. Therefore, it takes significant time to transfer the test patterns from the host computer 11 to the pattern memory 18 in the pattern generator 15.
Because the semiconductor test system is an expensive large scale computer system, it is necessary for a user to use the test system, in a most cost effective way. Further, in the semiconductor industry, there is always a strong demand in increasing the test efficiency to reduce the overall production cost of the semiconductor devices. Therefore, for operating the semiconductor test system with utmost efficiency, it has become important to reduce the time required for transfer the test patterns from the host to the pattern memory.